PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 44: Auto Refresh Mode
T0
CK#
CK
t
IS
t
IH
T1
T2
T3
T4
CK
t
CH
VALID
t
CL
((
))
((
))
((
))
((
))
Ta0
Ta1
((
))
((
))
((
))
((
))
Tb0
Tb1
Tb2
CKE
t
IS
t
IH
PRE
VALID
COMMAND
1
NOP 2
NOP2
NOP2
AR
((
))
((
))
((
))
((
))
NOP2, 3
AR 6
((
))
((
))
((
))
((
))
((
))
((
))
NOP2, 3
NOP2
ACT
A0-A9, A11
A12, A13
1
ALL BANKS
RA
A10
1
ONE BANK
((
))
((
))
RA
t
IS
t
IH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
1
Bank(s)4
BA
DQS
5
DQ
5
DM
5
tRP
tRFC
tRFC5
DON’T CARE
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active
during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after
t
RFC time, CKE must be active during clock positive tran-
sitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active
banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
-75
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
IH
F
MIN
0.45
0.45
7.5
10
.90
MAX
0.55
0.55
13
13
UNITS
t
CK
t
CK
ns
ns
ns
SYMBOL
t
IS
F
t
IH
S
t
IS
S
t
RFC
t
RP
MIN
.90
1
1
120
20
-75
MAX
UNITS
ns
ns
ns
ns
ns
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
