512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 28:
Deep Power-Down
T0
CK
t
IS
T1
T2
( (
Ta0
1
Ta1
Ta2
Ta3
))
((
))
t
CKE
CKE
((
))
T = 100µs
NOP
NOP
Vaild
3
COMMAND
NOP
DPD
2
((
))
((
))
All Banks idle with no
activity on the
data bus
Enter
deep
power-down mode
Exit
deep
power-down mode
DON’T
CARE
Notes:
1. Clock must be stable prior to CKE going HIGH.
2. DPD = Deep power-down mode command; PRE ALL = Precharge all banks.
3. Exit of deep power-down mode must be followed by the sequence described in the Deep
Power-Down” section on page 35.
In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the
following sequence is needed in order to enter a new command:
1. Maintain NOP input conditions for a minimum of 100µs.
2. Issue PRECHARGE commands for all banks.
3. Issue two or more AUTO REFRESH commands.
The values of the mode register and extended mode register will be retained upon
exiting deep power-down.
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figure 29 on page 37 and Figure 30 on page 37).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
