512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
WRITE with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank
m
will inter-
rupt a WRITE on bank
n
when registered, with the data-out appearing CL later. The
precharge to bank
n
will begin after
t
WR is met, where
t
WR begins when the READ to
bank
m
is registered. The last valid WRITE to bank
n
will be data-in registered one
clock prior to the READ to bank
m
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank
m
will
interrupt a WRITE on bank
n
when registered. The precharge to bank
n
will begin
after
t
WR is met, where
t
WR begins when the WRITE to bank
m
is registered. The last
valid data WRITE to bank
n
will be data registered one clock prior to a WRITE to bank
m
Figure 33:
WRITE With Auto Precharge Interrupted by a READ
T0
CLK
WRITE - AP
BANK
n
READ - AP
BANK
m
T1
T2
T3
T4
T5
T6
T7
COMMAND
BANK
n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
tWR - BANK
n
Precharge
tRP - BANK
n
tRP - BANK
m
Internal
States
BANK
m
Page Active
READ with Burst of 4
ADDRESS
DQ
BANK
n,
COL
a
D
IN
a
D
IN
a
+1
BANK
m,
COL
d
D
OUT
d
CL = 3 (bank
m)
D
OUT
d
+1
DON’T CARE
Notes:
1. DQM is LOW.
Figure 34:
WRITE With Auto Precharge Interrupted by a WRITE
T0
CLK
WRITE - AP
BANK
n
WRITE - AP
BANK
m
T1
T2
T3
T4
T5
T6
T7
COMMAND
BANK
n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
tWR - BANK
n
Precharge
tRP - BANK
n
t WR - BANK
m
Write-Back
Internal
States
BANK
m
Page Active
WRITE with Burst of 4
ADDRESS
DQ
BANK
n,
COL
a
D
IN
a
D
IN
a
+1
D
IN
a
+2
BANK
m,
COL
d
D
IN
d
D
IN
d
+1
D
IN
d
+2
D
IN
d
+3
DON’T CARE
Notes:
1. DQM is LOW.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
40
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©2005 Micron Technology, Inc. All rights reserved.
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