512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 29:
Clock Suspend During WRITE Burst
T0
CLK
T1
T2
T3
T4
T5
CKE
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK,
COL
n
D
IN
D
IN
n
D
IN
n
+1
D
IN
n
+2
DON’T CARE
Notes:
1. For this example, BL = 4 or greater, and DQM is LOW.
Figure 30:
Clock Suspend During READ Burst
T0
CLK
T1
T2
T3
T4
T5
T6
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK,
COL
n
DQ
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
DON’T CARE
Notes:
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
37
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©2005 Micron Technology, Inc. All rights reserved.
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