128Mb: x32 SDRAM
WRITE Operation
Figure 31: Alternating Bank Write Accesses
T0
CLK
tCKS
CKE
tCMS
Command
tCMH
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
tCK
tCKH
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS
DQM
tAS
Address
tAH
tCMH
Row
Column m
Row
Column b
Row
tAS
A10
tAH
Enable auto precharge
Row
Enable auto precharge
Row
Row
tAS
BA0, BA1
tAH
Bank 0
Bank 1
Bank 1
Bank 0
Bank 0
tDS
DQ
tRCD - bank 0
tRAS - bank 0
tRC - bank 0
tRRD
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
tWR - bank 0
tRP - bank 0
tRCD - bank 0
tWR - bank 1
tRCD - bank 1
Don’t Care
Note:
1. For this example, BL = 4.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
57
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2001 Micron Technology, Inc. All rights reserved.
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