128Mb: x32 SDRAM
PRECHARGE Operation
istered. The last valid data WRITE to bank
n
will be data registered one clock prior to a
WRITE to bank
m
(see Figure 41 (page 67)).
Figure 34: READ With Auto Precharge Interrupted by a READ
T0
CLK
Command
Bank n
NOP
READ - AP
Bank n
NOP
READ - AP
Bank m
NOP
NOP
NOP
NOP
T1
T2
T3
T4
T5
T6
T7
Page active
READ with burst of 4
Interrupt burst, precharge
tRP - bank n
Idle
tRP - bank m
Precharge
Internal
states
Bank m
Page active
READ with burst of 4
Address
DQ
Bank n,
Col a
Bank m,
Col d
D
OUT
CL = 3 (bank n)
CL = 3 (bank m)
D
OUT
D
OUT
D
OUT
Don’t Care
Note:
1. DQM is LOW.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
61
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2001 Micron Technology, Inc. All rights reserved.
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