128Mb: x32 SDRAM
WRITE Operation
Figure 33: WRITE – DQM Operation
T0
CLK
tCKS
CKE
tCMS
Command
tCMH
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
tCK
tCKH
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
ACTIVE
tCMS tCMH
DQM
tAS
Address
tAH
Column m
Enable auto precharge
Disable auto precharge
Row
tAS
A10
tAH
Row
tAS
BA0, BA1
tAH
Bank
Bank
tDS
DQ
tRCD
tDH
D
IN
tDS
tDH
D
IN
tDS
tDH
D
IN
Don’t Care
Note:
1. For this example, BL = 4.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
59
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2001 Micron Technology, Inc. All rights reserved.
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