1 MEG x 16
FPM DRAM
READ CYCLE
tRC
tRAS
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
V IH
V IL
tAR
tASR
V IH
V IL
tRAD
tRAH
tASC
tCAH
tRCD
tCAS
tCLCH
tRRH
tRP
RAS#
ADDR
ROW
tRCS
COLUMN
tRCH
ROW
WE#
V IH
V IL
tAA
tRAC
tCAC
tCLZ
tOFF
V
DQ V IOH
IOL
OPEN
t OE
VALID DATA
t OD
OPEN
OE#
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
t
AA
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CLCH
t
CLZ
t
CRP
t
CSH
t
OD
t
OE
-6
MAX
25
MIN
45
0
0
15
15
10
10
10
0
5
12
12
45
0
15
15
10,000
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
OFF
t
RAC
t
RAD
t
RAH
t
RAS
t
RC
t
RCD
t
RCH
t
RCS
t
RP
t
RRH
t
RSH
-5
MIN
0
9
9
50
84
11
0
0
30
0
13
10,000
MAX
12
50
12
10
60
104
14
0
0
40
0
15
MIN
0
-6
MAX
15
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
38
0
0
8
8
10
0
5
38
0
10,000
10,000
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
