1 MEG x 16
FPM DRAM
EARLY WRITE CYCLE
tRC
tRAS
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
tCAH
tRCD
tCAS
tCLCH
tRP
RAS#
ROW
COLUMN
tCWL
tRWL
tWCS
tWCR
tWCH
tWP
ROW
WE#
V IH
V IL
tDS
tDH
V
DQ V IOH
IOL
V IH
V IL
VALID DATA
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
t
AR
t
ASC
t
ASR
t
CAH
t
CAS
t
CLCH
t
CRP
t
CSH
t
CWL
t
DH
t
DS
t
RAD
-6
MAX
MIN
45
0
0
10,000
10
10
10
5
45
10
10
0
12
10,000
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
RAH
t
RAS
t
RC
t
RCD
t
RP
t
RSH
t
RWL
t
WCH
t
WCR
t
WCS
t
WP
-5
MIN
9
50
84
11
30
13
13
8
38
0
5
MAX
10,000
MIN
10
60
104
14
40
15
15
10
45
0
5
-6
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
38
0
0
8
8
10
5
38
8
8
0
9
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
