16Mb: 1 MEG x16
EDO DRAM
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving
RAS# HIGH for a minimum time of
t
RPS. This delay
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-to-
HIGH transition. If the DRAM controller uses a distrib-
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes a RAS#-ONLY or burst refresh sequence,
all 1,024 rows must be refreshed within the average
internal refresh rate, prior to the resumption of normal
operation.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within
t
REF (MAX), regardless of sequence.
The CBR, EXTENDED and SELF REFRESH cycles will
invoke the internal refresh counter for automatic RAS#
addressing.
An optional self refresh mode is available on the “S”
version. The self refresh feature is initiated by per-
forming a CBR REFRESH cycle and holding RAS# LOW
for the specified
t
RASS. The “S” option allows the user
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re-
fresh period of 128ms, or 125µs per row, when using a
WORD WRITE
RAS#
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
1
0
1
0
1
1
1
1
X = NOT EFFECTIVE (DON'T CARE)
Figure 3
WORD and BYTE WRITE Example
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc
MICRON [ MICRON TECHNOLOGY ]
