8 MEG x 8
EDO DRAM
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
V IH
V IL
tCSH
tRSH
tCRP
V IH
V IL
tAR
tRAD
tRAH
tASC
tCAH
tACH
tRCD
tCAS
tRP
RAS#
CAS#
tASR
ADDR
V IH
V IL
ROW
COLUMN
tRWD
tCWD
tAWD
tCWL
tRWL
tWP
ROW
tRCS
WE#
V IH
V IL
tAA
tRAC
tCAC
tCLZ
tDS
VALID D OUT
tOE
V IH
V IL
tOD
tDH
V
DQ V IOH
IOL
OPEN
VALID D IN
tOEH
OPEN
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
t
AA
t
ACH
t
AR
t
ASC
t
ASR
t
AWD
t
CAC
t
CAH
t
CAS
t
CLZ
t
CRP
t
CSH
t
CWD
t
CWL
t
DH
t
DS
-6
MAX
25
MIN
15
45
0
0
49
13
15
10
10
0
5
45
35
10
10
0
10,000
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t
OD
t
OE
t
OEH
t
RAC
t
RAD
t
RAH
t
RAS
t
RCD
t
RCS
t
RP
t
RSH
t
RWC
t
RWD
t
RWL
t
WP
-5
MIN
0
8
50
9
9
50
11
0
30
13
116
67
13
5
12
10
60
14
0
40
15
140
79
15
5
MAX
12
12
MIN
0
10
-6
MAX
15
15
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
12
38
0
0
42
8
8
0
5
38
28
8
8
0
10,000
10,000
10,000
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
