8 MEG x 8
EDO DRAM
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
CC
= +3.3V; f = 1
MHz; T
A
= 25°C.
3. I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
7. AC characteristics assume
t
T = 2.5ns.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
(or
between V
IL
and V
IH
).
9. In addition to meeting the transition rate
specification, all input signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
10. If CAS# and RAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12. Measured with a load equivalent to two TTL
gates and 100pF; and V
OL
= 0.8V and V
OH
= 2V.
13. If CAS# is LOW at the falling edge of RAS#,
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
CP.
14. The
t
RAD (MAX) limit is no longer specified.
t
RAD (MAX) was specified as a reference point
only. If
t
RAD was greater than the specified
t
RAD
(MAX) limit, then access time was controlled
exclusively by
t
AA (
t
RAC and
t
CAC no longer
applied). With or without the
t
RAD (MAX) limit,
t
AA,
t
RAC, and
t
CAC must always be met.
15. The
t
RCD (MAX) limit is no longer specified.
t
RCD (MAX) was specified as a reference point
only. If
t
RCD was greater than the specified
t
RCD
(MAX) limit, then access time was controlled
exclusively by
t
CAC (
t
RAC [MIN] no longer
applied). With or without the
t
RCD limit,
t
AA
and
t
CAC must always be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
t
WCS,
t
RWD,
t
AWD, and
t
CWD are not restrictive
18.
operating parameters.
t
WCS applies to EARLY
WRITE cycles. If
t
WCS >
t
WCS MIN, the cycle is an
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle.
t
RWD,
t
AWD and
t
CWD define READ-
MODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW results in a
LATE WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD are not applicable in a LATE
WRITE cycle.
19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
20. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
22. RAS#-ONLY REFRESH requires that all rows be
refreshed at least once every 64ms (4,096 rows
for the C2 version and 8,192 rows for the P4
version). CBR REFRESH requires that at least
4,096 cycles be completed every 64ms.
23. The DQs open during READ cycles once
t
OD or
t
OFF occur. If CAS# stays LOW while OE# is
brought HIGH, the DQs will open. If OE# is
brought back LOW (CAS# still LOW), the DQs
will provide the previously read data.
24. LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.
25. Column address changed once each cycle.
26. V
IH
overshoot: V
IH
(MAX) = V
CC
+ 2V for a pulse
width
≤
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
≤
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
27. NC pins are assumed to be left floating and are
not tested for leakage.
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
