8 MEG x 8
EDO DRAM
GENERAL DESCRIPTION (continued)
uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. Both devices provide EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
The 8 Meg x 8 DRAM must be refreshed periodically
in order to retain stored data.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 8 Meg x 8
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
t
CP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms in the noted
appendix).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. OE# can be brought LOW or HIGH
while CAS# and RAS# are LOW, and the DQs will
transition between valid data and High-Z. Using OE#,
there are two methods to disable the outputs and keep
them disabled during the CAS# HIGH time. The first
method is to have OE# HIGH when CAS# transitions
HIGH and keep OE# HIGH for
t
OEHC thereafter. This
will disable the DQs, and they will remain disabled
(regardless of the state of OE# after that point) until
CAS# falls again. The second method is to have OE#
LOW when CAS# transitions HIGH and then bring OE#
HIGH for a minimum of
t
OEP anytime during the CAS#
HIGH period. This will disable the DQs, and they will
remain disabled (regardless of the state of OE# after that
point) until CAS# falls again (see Figure 1). During
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. The data for
each location is accessed via the eight I/O pins (DQ0-
DQ7). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no write
will occur, and the data outputs will drive read data
from the accessed location.
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
tOD
tOES
VALID DATA (A)
VALID DATA (B)
tOD
tOEHC
VALID DATA (C)
tOD
VALID DATA (D)
OE#
V IH
V IL
tOE
tOEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL of DQs
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
