128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Read Configuration Register
Read Configuration Register
The read configuration register is a volatile, 16-bit read/write register used to select bus
read modes and to configure synchronous burst read behavior of the device.
The read configuration register is programmed using the PROGRAM READ CONFIGU-
RATION REGISTER command. To read the read configuration register, issue the READ
ID command and then read from offset 0005h.
Upon power-up or exit from reset, the read configuration register defaults to asynchro-
nous mode (RCR15 = 1; all other bits are ignored).
Table 10: Read Configuration Register Bit Definitions
Bit
15
14:11
Name
Read mode
Latency count
Description
0 = Synchronous burst mode
1 = Asynchronous mode (default)
0 0 1 1 = Code 3
0 1 0 0 = Code 4
0 1 0 1 = Code 5
0 1 1 0 = Code 6
0 1 1 1 = Code 7
1 0 0 0 = Code 8
1 0 0 1 = Code 9
1 0 1 0 = Code 10
1 0 1 1 = Code 11
1 1 0 0 = Code 12
1 1 0 1 = Code 13
Other bit settings are reserved; see the table below for supported
clock frequencies
0 = WAIT signal is LOW-true
1 = WAIT signal is HIGH-true
Write 0 to reserved bits
0 = WAIT de-asserted with valid data
1 = WAIT de-asserted one clock cycle before valid data
Write 0 to reserved bits
0 1 0 = 8-word burst, wrap only
0 1 1 = 16-word burst, wrap only
1 1 1 = Continuous-burst: linear, no-wrap only
Other bit settings are reserved
10
9
8
7:3
2:0
WAIT polarity
Reserved
WAIT delay
Reserved
Burst length
Table 11: Supported Clock Frequencies
Latency Count Code
3
4
5
6
Clock Frequency
V
CCQ
= 1.7V to 2.0V
≤32.6
MHz
≤43.5
MHz
≤54.3
MHz
≤65.2
MHz
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
26
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