128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Extended Configuration Register
Programming the Extended Configuration Register
The extended configuration register is programmed by issuing the PROGRAM EXTEN-
DED CONFIGURATION REGISTER command. The desired ECR[15:0] settings are
placed on A[15:0], while the PROGRAM EXTENDED CONFIGURATION REGISTER SET-
UP command is placed on the data bus. Upon issuing the SETUP command, the read
mode of the addressed partition is automatically changed to read status register mode.
Next, the CONFIRM command is placed on the data bus while the desired settings for
ECR[15:0] are again placed on A[15:0]. Upon issuing the CONFIRM command, the read
mode of the addressed partition is automatically switched to read array mode.
Because the desired ECR value is placed on the address bus, any hardware-connection
offsets between the host’s address outputs and the device’s address inputs must be tak-
en into account.
For example, if the host’s address outputs are aligned to the device’s address inputs
such that host address bit A1 is connected to address bit A0, the desired register value
must be left-shifted by one (for example, 2532h << 4A64h) before programming the
ECR.
Programming the ECR functions independently of the voltage on V
PP
.
Table 15: Program Extended Configuration Register Command Bus Cycles
Command
PROGRAM EXTENDED
CONFIGURATION
REGISTER
Setup WRITE Cycle
Address Bus
Register Data
Setup WRITE Cycle
Data Bus
0060h
Confirm WRITE Cycle Confirm WRITE Cycle
Address Bus
Data Bus
Register Data
0004h
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
29
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