128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Read Configuration Register
Table 11: Supported Clock Frequencies (Continued)
Latency Count Code
7
8
9
10
11
12
13
Clock Frequency
V
CCQ
= 1.7V to 2.0V
≤76.1
MHz
≤87.0
MHz
≤97.8
MHz
≤108.7
MHz
≤119.6
MHz
≤130.4
MHz
≤133.3
MHz
Programming the Read Configuration Register
The read configuration register is programmed by issuing the PROGRAM READ CON-
FIGURATION REGISTER command. The desired RCR[15:0] settings are placed on
A[15:0], while the PROGRAM READ CONFIGURATION REGISTER SETUP command is
placed on the data bus. Upon issuing the SETUP command, the read mode of the ad-
dressed partition is automatically changed to read status register mode.
Next, the CONFIRM command is placed on the data bus while the desired settings for
RCR[15:0] are again placed on A[16:1]. Upon issuing the CONFIRM command, the read
mode of the addressed partition is automatically switched to read array mode.
Because the desired read configuration register value is placed on the address bus, any
hardware-connection offsets between the host’s address outputs and the device’s ad-
dress inputs must be taken into account. For example, if the host’s address outputs are
aligned to the device’s address inputs such that host address bit A1 is connected to ad-
dress bit A0, the desired register value must be left-shifted by one (for example, 2532h
<< 4A64h) before programming the read configuration register
Synchronous read accesses cannot occur until both the device and the host are in syn-
chronous read mode. Therefore, the software instructions used to perform read config-
uration register programming and host chip select configuration must be guaranteed
not to fetch from the device (instructions must be in system RAM or locked in cache).
This also applies when switching back to asynchronous read mode from synchronous
read mode.
Table 12: PROGRAM READ CONFIGURATION REGISTER Bus Cycles
Command
PROGRAM READ
CONFIGURATION
REGISTER
Setup WRITE Cycle
Address Bus
RCR settings
Setup WRITE Cycle
Data Bus
0060h
Confirm WRITE Cycle Confirm WRITE Cycle
Address Bus
Data Bus
RCR settings
0003h
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
27
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