128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Common Flash Interface
Table 46: System Interface Information (Continued)
Hex
Offset
1Eh
Length
1
Description
V
PP
[programming] supply maximum program/
erase voltage
bits 0–3 BCD 100mV
bits 4–7 hex volts
n
such that typical single word program timeout
= 2
n
μs
n
such that typical full buffer write timeout = 2
n
μs
Address
1Eh
Hex
Code
- -95
ASCII Value
(DQ[7:0])
9.5V
1Fh
20h
1
1
1Fh
20h
- -06
64µs
- -0B (256,
2048µs (256,
512 Mbit -
512 Mbit -
90nm; 1024
90nm; 1024
Mbit -
Mbit - 65nm)
65nm)
1023µs (128,
- -0A (128, 256, 512 Mbit -
256, 512
65nm)
Mbit -
65nm)
- -0A
- -00
- -02
1s
NA
256µs
21h
22h
23h
24h
1
1
1
1
n
such that typical block erase timeout = 2
n
ms
n
such that typical full chip erase timeout = 2
n
ms
n
such that maximum word program timeout =
2
n
times typical
n
such that maximum buffer write timeout = 2
n
times typical
21h
22h
23h
24h
- -02 (256,
8192µs (256,
512 Mbit -
512 Mbit -
90nm; 128, 90nm; 128, 256,
256, 512
512 Mbit -
Mbit -
65nm)
65nm)
4096µs (1024
- -01 (1024 Mbit - 65nm)
Mbit -
65nm)
- -02
- -00
4s
NA
25h
26h
1
1
n
such that maximum block erase timeout = 2
n
times typical
n
such that maximum chip erase timeout = 2
n
times typical
25h
26h
Device Geometry Definition
Table 47: Device Geometry
Hex
Offset
27h
Length Description
1
n
such that device size in bytes = 2
n
.
Address
27:
Hex
Code
ASCII Value
(DQ[7:0])
(page 0
)
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
83
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