256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Test Conditions and Capacitance
AC Test Conditions and Capacitance
Figure 27: AC Input/Output Reference Timing
V
CCQ
Input V
CCQ
/2
0V
Test points
V
CCQ
/2 output
Note:
1. AC test inputs are driven at V
CCQ
for logic 1 and at 0V for logic 0. Input/output timing
begins/ends at V
CCQ
/2. Input rise and fall times (10% to 90%) <5ns. Worst-case speed oc-
curs at V
CC
= V
CC
(MIN).
Figure 28: Transient Equivalent Load Circuit
Device under
test
C
L
Notes:
Out
1. See the Test Configuration for Worst-Case Speed Conditions table for component values.
2. CL includes jig capacitance.
Table 42: Test Configuration: Worst-Case Speed Condition
Test Configuration
V
CCQ
(MIN) standard test
C
L
(pF)
30
Figure 29: Clock Input AC Waveform
t
CLK
CLK
V
IH
V
IL
t
CH/CL
t
FCLK/RCLK
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
82
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