64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 5:
READ Operation (ADV = LOW)
CE#
OE#
WE#
ADDRESS
ADDRESS VALID
DATA
LB#/UB#
DATA VALID
tRC = READ Cycle Time
DON’T CARE
Note:
ADV must remain LOW for page mode operation.
Figure 6:
WRITE Operation (ADV = LOW)
CE#
OE#
< tCEM
WE#
ADDRESS
DATA
ADDRESS VALID
DATA VALID
LB#/UB#
tWC = WRITE Cycle Time
DON’T CARE
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is per-
formed, then adjacent addresses can be read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the members of the 16-address Cellular-
RAM page. Any change in addresses A[4] or higher will initiate a new
t
AA access time.
that adjacent addresses can be read in a shorter period of time than random addresses.
WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be static (HIGH or LOW
– no transitions). CE# must be driven HIGH upon completion of a page mode access.
WAIT will be driven while the device is enabled and its state should be ignored. Page
mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page
mode read accesses.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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