64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 8:
Burst Mode READ (4-word Burst)
CLK
A[21:0]
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
READ Burst Identified
(WE# = HIGH)
D[0]
D[1]
D[2]
D[3]
Latency Code 2 (3 clocks)
ADDRESS
VALID
DON’T CARE
UNDEFINED
Note:
Non-default BCR settings for burst mode READ (4-word burst): Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
Figure 9:
Burst Mode WRITE (4-word Burst)
CLK
A[21:0]
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
WRITE Burst Identified
(WE# = LOW)
D[0]
D[1]
D[2]
D[3]
Latency Code 2 (3 clocks)
ADDRESS
VALID
DON’T CARE
Note:
Non-default BCR settings for burst mode WRITE (4-word burst): Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
12
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©2003 Micron Technology, Inc. All rights reserved.
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