MT8930C
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Preliminary Information
Intel microprocessor bus signals and timing. The
SNIC also has provisions for a controllerless mode
(Cmode=0), where the microprocessor port is
redefined to allow access to the control/status
registers via external hardware.
Channel 3 (B2)
B2
B2
B2
B2
B2
B2
Channel 2 (B1)
Don’t care
The three major blocks of the MT8930C, consisting
of the system serial interface (ST-BUS), HDLC
transceiver, and the digital subscriber loop interface
(S-interface) are interconnected by high speed data
busses.
Data sent to and received from the
S-interface port (B1, B2 and D channels) can be
accessed from either the parallel microprocessor
port or the serial ST-BUS port. This is also true for
SNIC control and status information (C-channel).
Depacketized D-channel information to and from the
HDLC section can only be accessed through the
parallel microprocessor port.
B2
B2
B2
B2
B2
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B1
B1
S-Bus Interface
The S-Bus is a four wire, full duplex, time division
multiplexed transmission facility which exchanges
information at 192 kbit/s rate including two 64 kbit/s
PCM voice or data channels, a 16 kbit/s signalling
channel and 48 kbit/s for synchronization and
overhead. The relative position of these channels
with respect to the ST-BUS is shown in Figures 4
and 5.
The SNIC makes use of the first four channels on the
ST-BUS to transmit and receive control/status and
data to and from the S-interface port. These are the
B, D and C-channels (see Figure 4).
The B1 and B2 channels each have a bandwidth of
64 kbit/s and are used to carry PCM voice or data
across the network.
The D-channel is primarily intended to carry
signalling information for circuit switching through
the ISDN network. The SNIC provides the capability
of having a 16 kbit/s or full 64 kbit/s D-channel by
allocating the B1-channel timeslot to the D-channel.
Access to the depacketized D-channel is only
granted through the parallel microprocessor port.
The C-channel provides a means for the system to
control and monitor the functionality of the SNIC.
This control/status channel is accessed by the
system through the ST-BUS or microprocessor
port.
The C-channel provides access to two
registers which provide complete control over the
state activation machine, the D-channel priority
mechanism as well as the various maintenance
functions. A detailed description of these registers is
discussed in the microprocessor port interface.
B1
B1
B1
B1
B1
B1
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C5
C6
C7
D7
D7
C7
C6
C5
Channel 1 (C)
D0
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DSTo
D0
Figure 4 - ST-BUS Channel Assignment
9-40
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DSTi
F0b
Only valid with 64 kbit/s D-channel
D6
D5
D5
D6
D2
D1
D1
D2
Channel 0 (D)
D4
D3
D3
D4
Output in high impedance state
B1
C0
C1
C2
C3
C4
C4
C3
C2
C1
C0
B1
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