MT8930C
Pin Description (continued)
Pin #
DIP
PLCC
Preliminary Information
Name
Description
17
26
SYNC/BA
Synchronization/Bus Activity Output (Cmode = 0):
output indicating synchronization
to incoming RX frames when activation request is asserted and the deactivation request
is ’0’ (AR = 1 and DR = 0). Synchronization is declared once three successive frames
conforming to the 14-bit bipolar violation criteria have been detected. If part is
deactivated or activation request is ’0’ (AR = 0 or DR = 1), this pin indicates the
presence of bus activity.
MFR
Multiframe Input/Output (Cmode=0):
multiframe input in NT mode or output in TE
mode. Setting this pin to one in NT mode when HALF = 1, forces the F
A
, N pair to 1, 0
respectively. This pin going high in TE mode indicates that F
A
= 1 & N= 0 has been
received. This signal is updated on the rising edge of the HALF signal.
Maintenance Channel (Q-channel) Input/Output (Cmode=0):
an output in NT mode
which is valid only in the frame following the transmission of MFR. In TE mode, this is
the maintenance channel (Q-channel) input which is transmitted in the F
A
and L bits
following the reception of the multiframe signal. This input is sampled on the falling
edge of the HALF signal.
M/S Input/Output (Cmode=0):
M/S bit input in NT mode or M/S bit output in TE mode.
M is read or written when HALF=1 while S is read or written when HALF=0.
Activate Request Input (Cmode = 0):
asserting AR with DR = 0 will initiate the
appropriate S-interface activation sequence coded in the NT or TE activation/
deactivation controller.
Deactivate Request Input (Cmode = 0):
asserting DR high will initiate the appropriate
S-interface deactivation sequence coded in the NT or TE activation/ deactivation
controller.
Reset Input:
Schmitt trigger reset input. If ’0’, sets all control registers to the default
conditions, resets activation state machines to the deactivated state, resets HDLC,
clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode.
18
30
19
31
MCH
20
21
32
34
M/S
AR
22
35
DR
23
37
Rsti
24
38
STAR/Rsto
Star/Reset (Open Drain Output):
192kbit/s Rx data output fixed relative to the ST-
BUS timebase. A group of NTs, in fixed timing mode, can be wire or’ed together to
create a Star configuration. Active low reset output in TE mode indicating 128
consecutive marks have been received. Can be connected directly to Rsti to allow NT
to reset all TEs on the bus. This pin must be tied to V
DD
with a 10 kΩ resistor.
LRx
Receive Line Signal Input:
this is a high impedance input for the pseudoternary line
signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and
21. A DC bias level on this input equal to V
Bias
must be maintained.
Transmit Line Signal Output:
this is a current source output designed to drive a
nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21.
Bias Voltage:
analog ground for Tx and Rx transformers. This pin must be decoupled
to V
DD
through a 10µF capacitor with good high frequency characteristics (i.e.,
tantalum).
Power Supply Input.
No Connection.
25
40
26
27
42
43
LTx
V
Bias
28
44
1,5-6,10-
12,15,18,
23,27-
29, 33,
36, 39, 41
V
DD
NC
9-38
MITEL [ MITEL NETWORKS CORPORATION ]
