ISO
2
-CMOS
V
Ref
An external voltage must be supplied to the V
Ref
pin
which provides the reference voltage for the digital
encoding and decoding of the analog signal. For
V
Ref
= 2.5V, the digital encode decision value for
overload (maximum analog signal detect level) is
equal to an analog input V
IN
= 2.415V (µ-Law
version) or 2.5V (A-Law version) and is equivalent to
a signal level of 3.17 dBm0 or 3.14 dBm0
respectively, at the codec.
The analog output voltage from the decoder at V
R
is
defined as:
µ-Law:
V
Ref
MT8960/61/62/63/64/65/66/67
driving a large number of codecs due to the high
Normal
input impedance of the V
Ref
input.
precautions should be taken in PCB layout design to
minimize noise coupling to this pin. A 0.1 µF
capacitor connected from V
Ref
to ground and located
as close as possible to the codec is recommended to
minimize noise entering through V
Ref
. This capacitor
should have good high frequency characteristics.
Timing
The codec operates in a synchronous manner (see
Figure 9a). The codec is activated on the first
positive edge of C2i after F1i has gone low. The
digital output at DSTo (which is a three-state output
driver) will then change from a high impedance state
to the sign bit of the encoded PCM word to be
output. This will remain valid until the next positive
edge, when the next most significant bit will be
output.
On the first negative clock edge (after F1i signal has
been internally synchronized and CA is at GNDD or
V
EE
) the logic signal present at DSTi will be clocked
into the input shift register as the sign bit of the
incoming PCM word.
The eight-bit word is thus input at DSTi on negative
edges of C2i and output at DSTo on positive edges
of C2i.
F1i must return to a high level after the eighth
clock pulse causing DSTo to enter high impedance
and preventing further input data to DSTi. F1i will
continue to be sampled on every positive edge of
C2i. (Note: F1i may subsequently be taken low
during the same sampling frame to enable entry of
serial data into CSTi. This occurs usually mid-frame,
in conjunction with CA=V
DD
, in order to enter an 8-bit
control word into Register B. In this case, PCM input
and output are inhibited by CA at V
DD
.)
X
[(
-0.5
128
) ( )(
16.5 + S
)]
33
+
±
V
2
C
128
±
V
OFFSET
A-Law:
V
Ref
X
+
[( )(
0.532 S
)]
2
C+1
128
OFFSET
C=0
V
Ref
X
[( )(
2
C
128
16.5 + S
32
)]
±
V
OFFSET
C≠0
where
C
= chord number (0-7)
S
= step number (0-15)
V
Ref
is a high impedance input with a varying
capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960
series of codecs is 2.5V ±0.5%. The output voltage
from the reference source should have a maximum
temperature coefficient of 100 ppm/C°. This voltage
should have a total regulation tolerance of ±0.5%
both for changes in the input voltage and output
loading of the voltage reference source. A voltage
reference circuit capable of meeting these
specifications is shown in Figure 5. Analog Devices
’AD1403A voltage reference circuit is capable of
NC
8
NC
7
NC
6
NC
5
V
Ref
0.1
µF
MT8960-67
FILTER/CODEC
AD1403A
1
2
3
4
NC
+5V
2.5V
Figure 5 - Typical Voltage Reference Circuit
6-23
MITEL [ MITEL NETWORKS CORPORATION ]
