MT8960/61/62/63/64/65/66/67
Internally the codec will then perform a decode cycle
on the newly input PCM word. The sampled and
held analog signal thus decoded will be updated 25
µs from the start of the cycle. After this the analog
input from the filter is sampled for 18 µs, after which
digital conversion takes place during the remaining
82 µs of the sampling cycle.
Since a single clock frequency of 2.048 MHz is
required, all digital data is input and output at this
rate. DSTo, therefore, assumes a high impedance
state for all but 3.9 µs of the 125 µs frame. Similarly,
DSTi input data is valid for only 3.9 µs.
ISO
2
-CMOS
Mode 2
CA= -5V (V
EE
); CSTi receives an eight-bit control
word
CSTi accepts a serial data stream synchronously
with DSTi (i.e., it accepts an eight-bit serial word in a
3.9 µs timeslot, updated every 125 µs, and is
specified
identically
to
DSTi
for
timing
considerations).
This eight-bit control word is
entered into Control Register A and enables
programming of the following functions: transmit and
receive gain, powerdown, loopback. Register B is
reset to zero and the SD outputs assume their
inactive state. Test modes cannot be entered.
Digital Control Functions
CSTi is a digital input (levels GNDD to V
DD
) which is
used to control the function of the filter/codec. It
operates in three different modes depending on the
logic levels applied to the Control Address input
(CA) and chip enable input (F1i) (see Table 1).
Mode 3
CA=0V (GNDD); CSTi receives an eight-bit control
word
As in Mode 2, the control word enters Register A and
the aforementioned functions are controlled. In this
mode, however, Register B is not reset, thus not
affecting the states of the SD outputs.
CA=+5V (V
DD
); CSTi receives an 8-bit control word
In this case the control word is transferred into
Register B. Register A is unaffected. The input and
output of PCM data is inhibited.
The contents of Register B controls the six
uncommitted outputs SD0-SD5 (four outputs, SD0-
SD3, on MT8960/61/64/65 versions of chip) and also
provide entry into one of the three test modes of the
chip.
FUNCTION
Mode 1
CA=-5V (V
EE
); CSTi=0V (GNDD)
The filter/codec is in normal operation with nominal
transmit and receive gain of 0dB. The SD outputs
are in their active states and the test modes cannot
be entered.
CA = -5V (V
EE
); CSTi = +5V (V
DD
)
A state of powerdown is forced upon the chip
whereby DSTo becomes high impedance, V
R
is
connected to GNDA and all analog sections have
power removed.
MODE
1
(Note 1)
2
CA
V
EE
V
EE
GNDD
CSTi
GNDD
V
DD
Serial
Data
3
(Note 2)
Serial
Data
V
DD
Note 1:
Note 2:
Serial
Data
Normal chip operation.
Powerdown.
Eight-bit control word into Register A. Register B is reset.
Eight-bit control word into register A. Register B is unaffected.
Eight-bit control word into register A. Register B is unaffected.
When operating in Mode 1, there should be only one frame pulse (F1i) per 125µs frame
When operating in Mode 3, PCM input and output is inhibited by CA=V
DD
.
Table 1. Digital Control Modes
6-24
MITEL [ MITEL NETWORKS CORPORATION ]
