MT8981D
ISO-CMOS
Hardware Description
Serial data at 2048 kbit/s is received at the four ST-
BUS inputs (STi0 to STi3), and serial data is
transmitted at the four ST-BUS outputs (STo0 to
STo3). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL’s
MT8964).
This serial input word is converted into parallel data
and stored in the 128 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams.
These locations can be read by the microprocessor
which controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS,
DTA, R/W and DS. There are two parts to any
address in the Data Memory or Connection
Memory. The higher order bits come from the
LOCATION
Control Register *
Channel 0
†
Channel 1
†
•
•
•
Channel 31
†
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.
In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus).
This bus
architecture can be used both in software-controlled
digital voice and data switching, and for
interprocessor communications.
The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
µs wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT8981 chip.
The MT8981 can switch data from channels on ST-
BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT8981 looks like a memory
peripheral. The microprocessor can write to the
MT8981 to establish switched connections between
input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-
BUS channels. By reading from the MT8981, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT8981 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS architecture.
A5
0
1
1
•
•
•
1
A4
X
0
0
•
•
•
1
A3
X
0
0
•
•
•
1
A2
X
0
0
•
•
•
1
A1
X
0
0
•
•
•
1
A0
X
0
1
•
•
•
1
HEX ADDRESS
00 - 1F
20
21
•
•
•
3F
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3 - Address Memory Map
2-20
MITEL [ MITEL NETWORKS CORPORATION ]
