MT8985
Pin Description
Pin #
Name
Description
40
44
44
DIP PLCC QFP
21
24
18
CS Chip Select (Input). Active low input enabling a microprocessor read or write of
control register or internal memories.
22-29 25-27 19-21 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data
29-33 23-27
in the internal control register, connect memory high, connect memory low and data
memory.
30
34 28
VSS Ground Rail.
31-38 35-39 29-33 STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These
41-43 35-37 STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s.
39
40
44
38
ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial
outputs. If this input is low STo0-7 are high impedance. If this input is high each
channel may still be put into high impedance by software control.
1
39
CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains
256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit
in the Connect Memory high locations.
6, 18, 12,22 NC No Connection.
28,
40
34,
44
automatically identifies the polarity and format of
frame synchronization input signals compatible to
ST-BUS and GCI interfaces.
Functional Description
With the integration of voice, video and data services
into the same network, there has been an increasing
demand for systems which ensure that data at N x 64
Kbit/s rates maintain frame sequence integrity while
being transported through time slot interchange
circuits. Existing requirements demand time slot
interchange devices performing switching with
constant throughput delay while guaranteeing
minimum delay for voice channels.
Device Operation
A functional block diagram of the MT8985 device is
shown in Figure 1. The serial ST-BUS streams
operate continuously at 2.048 Mb/s and are arranged
in 125 µs wide frames each containing 32 8-bit
channels. Eight input (STi0-7) and eight output
(STo0-7) serial streams are provided in the MT8985
device allowing a complete 256 x 256 channel non-
blocking switch matrix to be constructed. The serial
interface clock for the device is 4.096 MHz, as
required in ST-BUS and GCI specifications.
The MT8985 device provides both functions and
allows existing systems based on the MT8980D to
be easily upgraded to maintain the data integrity
while multiple channel data are transported. The
device is designed to switch 64 kbit/s PCM or N x 64
kbit/s data. The MT8985 can provide both frame
integrity for data applications and minimum
throughput switching delay for voice applications on
a per channel basis.
Data Memory
The received serial data is converted to parallel
format by the on-chip serial to parallel converters
and stored sequentially in a 256-position Data
Memory. The sequential addressing of the Data
Memory is generated by an internal counter that is
reset by the input 8 kHz frame pulse (F0i) marking
the frame boundaries of the incoming serial data
streams.
By using Mitel Message mode capability, the
microprocessor can access input and output time
slots on a per channel basis to control devices such
as the MITEL MT8972, ISDN Transceivers and T1/
CEPT trunk interfaces through the ST-BUS interface.
Different digital backplanes can be accepted by the
MT8985 device without user's intervention. The
MT8985 device provides an internal circuit that
Depending on the type of information to be switched,
the MT8985 device can be programmed to perform
2-47
MITEL [ MITEL NETWORKS CORPORATION ]
