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MT91L61AN 参数 Datasheet PDF下载

MT91L61AN图片预览
型号: MT91L61AN
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 - CMOS 3伏多功能的编解码器( MFC) [ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)]
分类和应用: 解码器编解码器
文件页数/大小: 32 页 / 148 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
MT91L60/61
frame. By arbitrarily assigning ST-BUS frame n as
the
reference
frame,
during
which
the
microprocessor D-Channel read and write operations
are performed, then:
COMMAND/ADDRESS

Œ
DATA INPUT/OUTPUT
Œ

COMMAND/ADDRESS:
DATA 1
RECEIVE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
DATA 1
TRANSMIT
SCLK
y
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CS
Ž
Œ
Delays due to internal processor timing which are transparent.

Ž
y
The MT91L60/L61:latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
Ž
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
X
X
A
2
A
1
X
X
4 bits - Unused
D
0
A
0
R/W
Figure 4 - Serial Port Relative Timing for Intel Mode 0
COMMAND/ADDRESS

Œ
DATA INPUT/OUTPUT
Œ

COMMAND/ADDRESS:
DATA 2
RECEIVE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA 1
TRANSMIT
SCLK
y
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Ž

Ž
Œ
Delays due to internal processor timing which are transparent .
y
The MT91L60/L61: latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
Ž
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
A
2
4 bits - Unused
X
X
R/W
X
A
1
D
0
A
0
X
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
7