MT91L60/61
125
µs
F0i
Advance Information
DSTi,
DSTo
CHANNEL 0
D-channel
LSB first
for D-
Channel
CHANNEL 1
C-channel
CHANNEL 2
B1-channel
CHANNEL 3
B2-channel
CHANNELS 4-31
Not Used
MSB first for C, B1- & B2-
Channels
FOod
Figure 6 - ST-BUS
(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 7a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 7a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
If no new data is written to address 04 hex , the
current D-channel register contents will be
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames F0i
input, whichever occurs first. To ensure D-Channel
data integrity, microport read/write access to
Address 04 hex must occur before the following
frame pulse. See Figure 7b for timing.
Channel Assignment
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 7c.
CEn - C-Channel
Channel 1 conveys the control/status information for
the Layer 1 transceiver. C-Channel data is
transferred MSB first on the ST-BUS by the
MT91L60/61. The full 64 kb/s bandwidth is available
and is assigned according to which transceiver is
being used. Consult the data sheet for the selected
transceiver for its C-Channel bit definitions and order
of bit transfer.
When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high.
Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.
If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).
8
MITEL [ MITEL NETWORKS CORPORATION ]
