MITSUBISHI
〈DIGITAL
ASSP〉
M66256FP
5120
×
8-BIT LINE MEMORY (FIFO)
• Matters that needs attention when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK
t
WCK
t
NWES
WE
t
DS
t
DH
t
DS
t
DH
D
n
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = “H”
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of
n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
6
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
