MITSUBISHI
〈DIGITAL
ASSP〉
M66256FP
5120
×
8-BIT LINE MEMORY (FIFO)
VARIABLE LENGTH DELAY BITS
• 1-line (5120 bits) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0
WCK
RCK
t
RESS
t
RESH
Cycle 1
Cycle 2
Cycle 5118 Cycle 5119
Cycle 5120 Cycle 5121 Cycle 5122
(0')
(1')
(2')
WRES
RRES
t
DS
t
DH
t
DS
t
DH
D
n
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycles
t
AC
t
OH
Q
n
(0)
(1)
(2)
(3)
WE, RE = “L”
• N-bit delay bit
(Making a reset at a cycle corresponding to delay length)
Cycle 0
WCK
RCK
t
RESS
t
RESH
Cycle 1
Cycle 2
Cycle n–2
Cycle n–1
Cycle n
(0')
Cycle n+1 Cycle n+2
(1')
(2')
Cycle n+3
(3')
t
RESS
t
RESH
WRES
RRES
t
DS
t
DH
t
DS
t
DH
D
n
(0)
(1)
(2)
(n–3)
(n–2)
(n–1)
(0')
(1')
(2')
(3')
m cycles
t
AC
t
OH
Q
n
(0)
(1)
(2)
(3)
WE, RE = “L”
m
≥
3
8
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
