MITSUBISHI <DIGITAL ASSP>
M66282FP
8192 x 8-BIT LINE MEMORY
•
Matters that needs attetion when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK
t
WCK
t
NWES
WEB
t
DS
t
DH
t
DS
t
DH
Dn
(n)
(n)
Period for writing data
(n) into memory
Period for writing data
(n) into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1
cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
7
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
