MITSUBISHI <DIGITAL ASSP>
M66282FP
8192 x 8-BIT LINE MEMORY
VARIABLE LENGTH DELAY BIT
•
1 line (8192 bits) delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read
cycle to easily make 1 line delay.
0 cycle
WCK
RCK
t
RESS
t
RESH
WRESB
RRESB
1 cycle
2 cycle
8190 cycle 8191 cycle
8192 cycle 8193 cycle 8194 cycle
(0')
(1')
(2')
t
DS
t
DH
Dn
(0)
(1)
(2)
(8189)
(8190)
(8191)
t
DS
t
DH
(0')
(1')
(2')
(3')
8192 cycle
Qn
t
AC
t
OH
(0)
(1)
(2)
(3)
WEB, REB = "L"
•
n-bit delay bit
(Reset at cycles according to the delay length)
0 cycle
WCK
RCK
t
RESS
t
RESH
WRESB
RRESB
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle
(0')
n+1 cycle
(1')
n+2 cycle
(2')
n+3 cycle
(3')
t
RESS
t
RESH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n-3)
(n-2)
(n-1)
t
DS
t
DH
(0')
(1')
(2')
(3')
m cycle
Qn
t
AC
t
OH
(0)
(1)
(2)
(3)
WEB, REB = "L"
9
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
