V62C21164096
NOTES:
1. The internal write time of the memory is defined by the overlap of CE
1
and CE
2
active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2. t
WR
is measured from the earlier of CE
1
or WE going high, or CE
2
going LOW at the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = V
IL
or V
IH
. However it is recommended to keep OE at V
IH
during write cycle to avoid bus contention.
5. If CE
1
is LOW and CE
2
is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6. t
CW
is measured from CE
1
going low or CE
2
going HIGH to the end of write.
7. CE
2
is available on BGA package only.
V62C21164096 Rev. 1.6 October 2001
CILETIV LESOM
ADDRESS
CE
1
CE
2
WE
OUTPUT
INPUT
ADDRESS
CE
1
CE
2
WE
OUTPUT
INPUT
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
(4, 7)
t
WC
t
WR(2)
t
CW(6)
t
AW
t
CW(6)
t
AS
t
WP(1)
t
WHZ
t
DW
t
DH
Write Cycle 2 (CE Controlled)
(4, 7)
t
WC
t
CW(6)
(4)
t
WR(2)
t
AW
t
CW(6)
t
AS
High-Z
t
DW
t
DH
(5)
8
MOSEL [ MOSEL VITELIC, CORP ]
