V62C21164096
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Write Enable Input
WE
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O
1
–I/O
16
Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
GND
Power Supply
Ground
A
0
–A
17
Address Inputs
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
CE
1
, CE
2
* Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The output enable input is active LOW. With chip
enabled, when OE is Low and WE High, data will
be presented on the I/O pins. The I/O pins will be in
the high impedance state when OE is High.
*CE
2
is available on BGA package only.
CILETIV LESOM
Pin Descriptions
A4
A3
A2
A1
A0
CE
1
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin Configurations (Top View)
44-Pin TSOP-II (Standard)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UBE
LBE
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A17
48 BGA
1
A
B
C
D
E
F
G
H
2
3
4
5
6
A
B
1
BLE
I/O9
2
OE
BHE
3
A0
A3
4
A1
A4
A6
A7
5
A2
6
CE
2
CE
1
I/O1
I/O2 I/O3
I/O4 VCC
C I/O10 I/O11 A5
D
E
F
VSS I/O12 A17
VCC I/O13 NC
A16 I/O5 VSS
I/O15 I/O14 A14 A15 I/O6 I/O7
NC
A8
A12 A13
A9
WE
I/O8
NC
G I/O16
H
NC
A10 A11
Note:
NC means no connect.
TOP VIEW
TOP VIEW
V62C21164096 Rev. 1.6 October 2001
2
MOSEL [ MOSEL VITELIC, CORP ]
