4.6.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals.
EXTRST (external reset) drives the external reset pin.
CLKRST (clock reset) resets the clock module.
MSTRST (master reset) goes to all other internal circuits.
SYSRST (system reset) indicates to internal circuits that the CPU has executed
a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure; thus the reset
control logic responds by asserting reset to the system immediately. (A system reset,
however, caused by the CPU32 RESET instruction, is asynchronous but does not in-
dicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The inter-
nal bus monitor is automatically enabled for synchronous resets. When a bus cycle
does not terminate normally, the bus monitor terminates it.
Refer to
for a summary of reset sources.
Table 4-15 Reset Source Summary
Type
External
Power Up
Software Watchdog
HALT
Loss of Clock
Test
System
Source
External
EBI
Monitor
Monitor
Clock
Test
CPU32
Timing
Synch
Asynch
Asynch
Asynch
Synch
Synch
Asynch
Cause
External Signal
V
DD
Time Out
Internal HALT Assertion
(e.g. Double Bus Fault)
Loss of Reference
Test Mode
RESET Instruction
Reset Lines Asserted by Controller
MSTRST
CLKRST
EXTRST
MSTRST
CLKRST
EXTRST
MSTRST
MSTRST
MSTRST
MSTRST
—
CLKRST
CLKRST
CLKRST
—
—
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
1.
2.
3.
4.
4
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in
4.6.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions.
is a summary of reset mode selection options.
MC68331
USER’S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
4-37
MOTOROLA [ MOTOROLA, INC ]
