MU9C RCP Family
Packet Stream
C ontroller
Switch C ontrol
And Packet
D ata
RCP
C ontrol
N etwork
Address
D ata
Switch
Fabric
R AM
Address
M U 9C
R AM
Figure 2: Switch Block Diagram
PIN DESCRIPTIONS
Note:
Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM
architecture draws substantial currents during compare operations, mandating the use of good layout and bypassing techniques. Refer
to the Electrical Characteristics section for more information.
DQ31-0 (Data Bus, Three-state, Common
Input/ Output)
The DQ31-0 lines convey data to and from the MU9C
RCP. When the /E input is HIGH the DQ31-0 lines are
held in their high-impedance state. The /W input deter-
mines whether data flows to or from the device on the
DQ31-0 lines. The source or destination of the data is
determined by the AC bus, DSC, and the /AV line. During
a Write cycle, data on the DQ31-0 lines is registered by the
falling edge of /E.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 31-0
(DSC LOW) or bits 63-32 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA12-0/AA11-0 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address cycle into an already full system, the lowest-pri-
ority device will drive the AA bus with all 1s. The AA bus
is latched when /E is LOW, and are free to change only
when /E is HIGH.
3
AC12-0/AC11-0 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MU9C RCP, depend-
ing on the state of the /AV input. When /AV is LOW then
the AC bus carries an address; when /AV is HIGH the AC
bus carries control information. Data on the AC bus is reg-
istered by the falling edge of /E. When software control is
selected, the state of the AC bus does not affect the opera-
tion of the device.
Rev. 8.04
MUSIC [ MUSIC SEMICONDUCTORS ]
