MU9C8328 Ethernet Interface
APPLICATIONS
Connections
Connection diagrams are shown in Figures 2, 3, and 4 for
National’s SONIC, AMD’s MACE, and Motorola’s
QUICC Ethernet controller chips. Other controller chips
that provide a serial NRZ received data port and clock
can also be used in similar fashions. The /NETRDY line
is provided for controller chips that output data on the
received data line while transmitting. If /NETRDY is
deasserted, the internal network state machine will safely
complete any current activity and then wait until
/NETRDY is asserted again before parsing another frame.
If the controller chip does not output data on the received
data line while transmitting, /NETRDY may be tied to
ground, and the MU9C8328’s valid clock detector will
determine when it is time to start parsing a frame.
Initialization of the LANCAM
Before using, the MUSIC LANCAMs need to be configured
for the number of LANCAMs in a daisy chain and for the
filtering conditions in the Control and Segment Control
registers. Before configuring the LANCAMs, bit 13 in the
MU9C8328 Control register needs to be set to 0, to turn off
network filtering. Table 3 shows the steps for configuring
two LANCAMs in a daisy chain. The routine selects register
05H in the MU9C8328, which sends Command Write cycles
to the LANCAM. The sequence shown resets the LANCAMs,
sets the Page address for both LANCAMs in the daisy chain,
then sets the Control and Segment Control registers. If a
Mask register were needed, then the sequence would be
modified to set the Persistent destination to MR1 or MR2,
use MU9C8328 register 06H to write data into the Mask
register, change the final Control register value to 8050H or
8060H instead of 8040H to invoke MR1 or MR2 during
compares, and then resetting the Persistent destination to
L A N CA M
L A N CA M
/E
/CM
/W
/E C
/M F
/FF
/E
/CM
/W
/E C
/M F
/FF
DQ(15- 0)
DQ(15- 0)
A M 79C 940
/E
/CM
/W
/E C
/M F
/FF
S Y S CLK
/RE S E T
D P83932
/E
/CM
/W
/E C
/M F
/FF
S Y S CLK
/RE S E T
S RDC LK
S E RCLK
/CS
RX Co
/AS
/W E
A(2-0)
S E RCLK
/CS
/AS
S RD
S E RDAT
M U 9C 8328
RX Do
S E RDAT
M U 9C 8328
/W E
A(2-0)
TX E N
/NE TRD Y
D(15- 0)
TX E
/NE TRD Y
D(15- 0)
RE ADY
/INT
/E AM /R
/RE JE C T
RE ADY
/INT
/P RE J
/RE JE C T
Figure 2: AMD’s MACE™ Connection Diagram
Figure 3: National’s SONIC™ Connection Diagram
L A N CA M
M C 68 1 6 0
EE ST
RCL K RX
RE NA
/E
/CM
/W
/E C
/M F
/FF
S Y S CLK
/RE S E T
/CS
S E RDAT
/NE TRD Y
/AS
/W E
/E
/CM
/W
/E C
/M F
/FF
DQ(15- 0)
S E RCLK
M U 9C 8328
RCL K RX D
RE NA
/RR JCT
/RE JE C T
A(2-0)
D(15- 0)
RE ADY
/INT
M C 68 3 6 0
Q U IC C
Figure 4: Motorola’s QUICC™ Connection Diagram
Rev. 4a
8
MUSIC [ MUSIC SEMICONDUCTORS ]
