MU9C8328 Ethernet Interface
FUNCTIONAL DESCRIPTION
The MU9C8328 works with the MUSIC LANCAMs to
provide a complementary and versatile 10 MHz Ethernet
filtering solution for bridges, routers, and switches. Using
the serial NRZ data stream and clock available from many
Ethernet controller chips, the MU9C8328 parses the
incoming frame, finds the Start Delimiter, and forms the
Destination and Source addresses into 16-bit words for
relay to the LANCAM. After all three 16-bit DA segments
have been loaded into the LANCAM, an automatic
compare occurs between the incoming DA and the 48-bit
MAC addresses stored in the LANCAM. If a match is
found, the MU9C8328 is notified, and if Control Register
bit 5 is set for negative filtering, the /REJECT line will be
asserted if Control Register bit 3 is set. An interrupt can
also be generated over the /INT pin if Control Register bit
8 is set. Also, if Control Register bit 0 is set, the Associated
data in segment 0 of the matching entry in the LANCAM
will be retrieved and stored in the Associated Data register
for reading by the host processor. If a match is not found
on the DA, and Control Register bit 5 was set for positive
filtering, the /REJECT line will be asserted. An interrupt
can also be enabled for a no-match on a DA using Control
Register bit 10.
After the DA filtering, the Source Address is loaded
into the LANCAM in three segments. Upon the last
SA load, an automatic compare again takes place. If
there is a match between the SA and an entry in the
CAM, and Control Register bit 7 was set, an interrupt
is asserted. Positive and negative filtering on the SA is
also possible, set by Control Register bit 4, and the /INT
pin may be asserted as well. In the case of a no-match
on an SA, the SA can be automatically “learned” (i.e.,
moved to the first empty location in the LANCAM) if
Control Register bit 1 is set.
If a Loss of Carrier is detected by SERCLK staying LOW
for more than 16 SYSCLK cycles, an interrupt is triggered
if Control Register bit 12 is set. This interrupt also activates
if a collision is detected.
The host processor can access the MU9C8328, shown in
Table 1, at any time, even when a frame is being processed.
Access to the LANCAM through the LANCAM access
registers (04H to 07H) is arbitrated, however, with the
network having precedence. The host processor can have
control of the LANCAM by setting the Network Enable
bit in the Control register (bit 13) to a 0, which will disable
network filtering until it is returned to a 1. While disabled,
bit 14 in the Control register sets the MU9C8328 to accept
all frames by keeping /REJECT HIGH, or to reject all
frames by keeping /REJECT LOW.
Registers 04H through 07H allow the host processor access
to the LANCAM for Command and Data Write and Read
cycles, with /EC HIGH or LOW. This is often needed for
housekeeping activities, such as preventing the LANCAM
from becoming full by aging out old entries based on
timestamps stored in the Associated data (Segment 0) of
the LANCAM memory.
The /INT pin will go LOW at the end of the SA field to
indicate an interrupt for any of the reasons set in the
Control register. Reading the Status register to discover
the nature of the interrupt will take the /INT pin HIGH
again. The READY signal goes LOW after a host processor
write to a register or the LANCAM to indicate that the
Write cycle has begun and return HIGH after a fixed
number of SYSCLK cycles. It will also go LOW during a
read from the LANCAM and return HIGH when the data
from the LANCAM is valid. Since a network compare
activity has precedence over a host process access to the
LANCAM, READY will stay LOW until the network
activity is complete and the host-induced LANCAM read
has completed.
Figure 1 shows a typical network filtering sequence, where
the MU9C8328’s Control register was set to 2109H. This
setting enables network filtering, enables an interrupt for
a match found on the DA, enables negative filtering on
the DA (reject if a DA match is found), enables asserting
the /REJECT pin for compares on the DA, and enables
retrieving the Associated Data field from the matching
location in the LANCAM.
5
Rev. 4a
MUSIC [ MUSIC SEMICONDUCTORS ]
