MU9C8328 Ethernet Interface
APPLICATIONS
Continued
the Comparand register as shown in Table 3. If only one
LANCAM is used, Figure 1 would be modified to replace
steps 8 through 13 with a TCO DS (0228H) followed by
a 0000H.
Enabling Network Activity
Responding to Interrupts
After the LANCAMs have been initialized, the MU9C8328
is enabled to begin processing network traffic by setting
bit 13 (NETEN) in its Control register to a 1 along with
the desired filtering actions and interrupt enables.
Step A(2–0)
0H
1
5H
2
5H
3
5H
4
5H
5
5H
6
5H
7
5H
8
5H
9
5H
10
5H
11
5H
12
5H
13
5H
14
5H
15
5H
16
5H
17
5H
18
5H
19
5H
20
5H
21
5H
22
5H
23
5H
24
5H
25
5H
26
5H
27
5H
28
7H
29
7H
30
7H
31
7H
32
5H
33
5H
34
5H
35
5H
36
0H
37
/WE Mnemonic D(15–0)
C000H
L
0000H
H
0228H
TCO_DS
L
FFFFH
L
0200H
TCO_CT
L
0000H
L
0208H
TCO_PA
L
0000H
L
0700H
SFF
L
0208H
TCO_PA
L
0001H
L
0700H
SFF
L
0200H
TCO_CT
L
0000H
L
0619H
SBR
L
0200H
TCO_CT
L
8111H
L
0210H
TCO_SC
L
0000H
L
SPD_MR1 0108H
L
FFF0H
L
0100H
SPD_CR
L
0618H
SFR
L
0200H
TCO_CT
L
8041H
L
SPD_MR1 0108H
L
0210H
TCO_SC
L
1C04H
L
FFF0H
L
FFFFH
L
FFFFH
L
FFFFH
L
0100H
SPD_CR
L
0210H
TCO_SC
L
3808H
L
0005H
SPS_HM
L
FC8AH
L
Depending on the filtering or error interrupt conditions
set in the MU9C8328 Control Register, the /INT line will
assert at the end of the frame SA field. The host can then
read the MU9C8328 Status register to determine the cause
of the interrupt, whereupon the Status register is reset. If
there was a DA match interrupt and read associated data
was set, then the associated data segment stored in the
LANCAM at the same location that matched the frame’s
DA can be read out of the Associated Data register (03H).
Comments
Pass all frames during initialization
Command Read to reset LANCAM state machines
Selects all Device Select registers
Selects all LANCAMs
Selects all Control registers
Resets all memory locations
Selects first Page Address register
Writes first Page Address value
Sets Full flag on first LANCAM
Selects second Page Address register
Writes second Page Address value
Sets Full flag on second LANCAM
Selects all Control registers
Resets all Full flags
Select Background Register set
TCO CT
48RAM, 16CAM, MR1, Enhanced mode
Select Segment Control register
Set Read and Write to segment 0
Set Persistent Destination to Mask Register 1
Setup Time Stamp in lowest 4 bits of segment 0
Set Persistent Destination to Comparand register
Select Foreground Register set
Select Command register
48CAM, 16RAM, No Mask, Enhanced mode
Set Persistent Destination to Mask Register 1
Select Segment Control register
Set to write Segments 0, 1, 2, and 3
Write to Segment 0 of MR1
Write to Segment 1 of MR1
Write to Segment 2 of MR1
Write to Segment 3 of MR1
Set Persistent Destination to Comparand register
Select Segment Control register
Write Segments 1–3, Read Segment 0
Set Persistent source to Highest match
Enable filter, Negative filter on DA, enable learn
Table 3: LANCAM Initialization Code
9
Rev. 4a
MUSIC [ MUSIC SEMICONDUCTORS ]
