Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
e a
e b
25 C. All other limits are assured by correlation with other
e
5.0V 5%, T
g
5.0V 5%, V
g
CC
BB
A
e
production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at V
0 C to 70 C by correlation with 100% electrical testing at T
§
§
§
A
e
CC
a
e b
e
e
e
0.7V.
OL
5.0V, V
5.0V, T
25 C. All timing parameters are measured at V
2.0V and V
§
See Definitions and Timing Conventions section for test methods information.
BB
A
OH
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1/t
Frequency of Master Clock
1.536
1.544
MHz
MHz
MHz
PM
MCLK and MCLK
X
2.048
R
R
R
t
t
t
t
t
t
t
t
Rise Time of Master Clock
Fall Time of Master Clock
Period Bit of Clock
MCLK and MCLK
X
50
50
ns
ns
ns
ns
ns
ns
ns
ns
RM
FM
PB
RB
FB
MCLK and MCLK
X
485
488
15725
50
Rise Time of Bit Clock
Fall Time of Bit Clock
BCLK and BCLK
X R
BCLK and BCLK
X
50
R
Width of Master Clock High
Width of Master Clock Low
MCLK and MCLK
X
160
160
100
WMH
WML
SBFM
R
MCLK and MCLK
X
R
Set-Up Time from BCLK High
X
to MCLK Falling Edge
X
t
Set-Up Time from FS High
X
Long Frame Only
100
ns
SFFM
to MCLK Falling Edge
X
t
t
t
Width of Bit Clock High
Width of Bit Clock Low
160
160
0
ns
ns
ns
WBH
WBL
HBFL
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
Short Frame Only
Long Frame Only
t
t
t
Holding Time from Bit Clock
High to Frame Sync
0
80
0
ns
ns
ns
HBFS
SFB
Set-Up Time for Frame Sync
to Bit Clock Low
e
Load 150 pF plus 2 LSTTL Loads
Delay Time from BCLK High
X
180
DBD
to Data Valid
e
Load 150 pF plus 2 LSTTL Loads
t
t
Delay Time to TS Low
X
140
165
ns
ns
DBTS
Delay Time from BCLK Low to
X
50
20
DZC
Data Output Disabled
e
C
L
t
Delay Time to Valid Data from
0 pF to 150 pF
165
ns
DZF
FS or BCLK , Whichever
X X
Comes Later
t
t
t
t
t
Set-Up Time from D Valid to
R
50
50
ns
ns
ns
ns
ns
SDB
HBD
SF
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-Up Time from FS
X/R
to
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
BCLK
X/R
Low
Hold Time from BCLK
X/R
Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
100
HF
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
HBFI
(FS or FS
X
)
R
t
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
WFL
7
NSC [ National Semiconductor ]
