Functional Description
POWER-UP
When power is first applied power-on reset circuitry initializ-
es the COMBO
TM
and places it into a power-down state All
non-essential circuits are deactivated and the D
X
VF
R
O
VPO
b
and VPO
a
outputs are put in high impedance states
To power-up the device a logical low level or clock must be
applied to the MCLK
R
PDN pin
and
FS
X
and or FS
R
pulses
must be present Thus 2 power-down control modes are
available The first is to pull the MCLK
R
PDN pin high the
alternative is to hold both FS
X
and FS
R
inputs continuously
low the device will power-down approximately 2 ms after
the last FS
X
or FS
R
pulse Power-up will occur on the first
FS
X
or FS
R
pulse The TRI-STATE PCM data output D
X
will remain in the high impedance state until the second FS
X
pulse
SYNCHRONOUS OPERATION
For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLK
X
and the MCLK
R
PDN pin can be used as a power-down
control A low level on MCLK
R
PDN powers up the device
and a high level powers down the device In either case
MCLK
X
will be selected as the master clock for both the
transmit and receive circuits A bit clock must also be ap-
plied to BCLK
X
and the BCLK
R
CLKSEL can be used to
select the proper internal divider for a master clock of 1 536
MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation
the device automatically compensates for the 193rd clock
pulse each frame
With a fixed level on the BCLK
R
CLKSEL pin BLCK
X
will be
selected as the bit clock for both the transmit and receive
directions Table I indicates the frequencies of operation
which can be selected depending on the state of BCLK
R
CLKSEL In this synchronous mode the bit clock BCLK
X
may be from 64 kHz to 2 048 MHz but must be synchro-
nous with MCLK
X
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
After 8
bit clock periods the TRI-STATE D
X
output is returned to a
high impedance state With an FS
R
pulse PCM data is
latched via the D
R
input on the negative edge of BCLK
X
(or
BCLK
R
if running) FS
X
and FS
R
must be synchronous with
MCLK
X R
TABLE I Selection of Master Clock Frequencies
Master Clock
Frequency Selected
TP3067
Clocked
0
1
2 048 MHz
1 536 MHz or
1 544 MHz
2 048 MHz
TP3064
1 536 MHz or
1 544 MHz
2 048 MHz
1 536 MHz or
1 544 MHz
sion performance however MCLK
R
should be synchronous
with MCLK
X
which is easily achieved by applying only static
logic levels to the MCLK
R
PDN pin This will automatically
connect MCLK
X
to all internal MCLK
R
functions (see Pin
Description) For 1 544 MHz operation the device automati-
cally compensates for the 193rd clock pulse each frame
FS
X
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
BCLK
R
must be a
clock the logic levels shown in Table I are not valid in asyn-
chronous mode BCLK
X
and BCLK
R
may operate from 64
kHz to 2 048 MHz
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the
same as the TP3020 21 CODECs) or a long frame sync
pulse Upon power initialization the device assumes a short
frame mode In this mode both frame sync pulses FS
X
and
FS
R
must be one bit clock period long with timing relation-
ships specified in
Figure 2
With FS
X
high during a falling
edge of BCLK
X
the next rising edge of BCLK
X
enables the
D
X
TRI-STATE output buffer which will output the sign bit
The following seven rising edges clock out the remaining
seven bits and the next falling edge disables the D
X
output
With FS
R
high during a falling edge of BCLK
R
(BCLK
X
in
synchronous mode) the next falling edge of BCLK
R
latches
in the sign bit The following seven falling edges latch in the
seven remaining bits All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode
LONG FRAME SYNC OPERATION
To use the long (TP5116A 56 CODECs) frame mode both
the frame sync pulses FS
X
and FS
R
must be three or more
bit clock periods long with timing relationships specified in
Figure 3
Based on the transmit frame sync FS
X
the COM-
BO will sense whether short or long frame sync pulses are
being used For 64 kHz operation the frame sync pulse
must be kept low for a minimum of 160 ns The D
X
TRI-
STATE output buffer is enabled with the rising edge of FS
X
or the rising edge of BCLK
X
whichever comes later and the
first bit clocked out is the sign bit The following seven
BCLK
X
rising edges clock out the remaining seven bits The
D
X
output is disabled by the falling BCLK
X
edge following
the eighth rising edge or by FS
X
going low whichever
comes later A rising edge on the receive frame sync pulse
FS
R
will cause the PCM data at D
R
to be latched in on the
next eight falling edges of BCLK
R
(BCLK
X
in synchronous
mode) All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see
Figure 4
The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The A D is of companding type according to
m-law
(TP3064) or A-law (TP3067) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t
MAX
) of nominally 2 5V peak (see
BCLK
R
CLKSEL
ASYNCHRONOUS OPERATION
For asynchronous operation separate transmit and receive
clocks may be applied MCLK
X
and MCLK
R
must be 2 048
MHz for the TP3067 or 1 536 MHZ 1 544 MHz for the
TP3064 and need not be synchronous For best transmis-
3
NSC [ NATIONAL SEMICONDUCTOR ]
