Functional Description
(Continued)
table of Transmission Characteristics) The FS
X
frame sync
pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through D
X
at the next FS
X
pulse The total encoding delay will be ap-
proximately 165
ms
(due to the transmit filter) plus 125
ms
(due to encoding delay) which totals 290
ms
Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3067) or
m-law
(TP3064) and the 5th order low pass filter corrects for
the sin x x attenuation due to the 8 kHz sample hold The
filter is then followed by a 2nd order RC active post-filter
with its output at VF
R
O The receive section is unity-gain
but gain can be added by using the power amplifiers Upon
the occurrence of FS
R
the data at the D
R
input is clocked in
on the falling edge of the next eight BCLK
R
(BCLK
X
) peri-
ods At the end of the decoder time slot the decoding cycle
begins and 10
ms
later the decoder DAC output is updated
The total decoder delay is
E
10
ms
(decoder update) plus
110
ms
(filter delay) plus 62 5
ms
( frame) which gives
approximately 180
ms
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer The gain of
the first power amplifier can be adjusted to boost the
g
2 5V
peak output signal from the receive filter up to
g
3 3V peak
into an unbalanced 300X load or
g
4 0V into an unbal-
anced 15 kX load The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads
Maximum power transfer to a 600X subscriber line termina-
tion is obtained by differentially driving a balanced trans-
former with a
S
2 1 turns ratio as shown in
Figure 4
A total
peak power of 15 6 dBm can be delivered to the load plus
termination
ENCODING FORMAT AT D
X
OUTPUT
TP3064
m-Law
V
IN
e a
Full-Scale
V
IN
e
0V
V
IN
e b
Full-Scale
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
TP3067
A-Law
(Includes Even Bit Inversion)
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
4
NSC [ NATIONAL SEMICONDUCTOR ]
