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M25PX64 参数 Datasheet PDF下载

M25PX64图片预览
型号: M25PX64
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 66 页 / 1330 K
品牌: NUMONYX [ NUMONYX B.V ]
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Instructions
M25PX64
6.6
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on serial data output (DQ1), each bit being shifted out, at a maximum
frequency f
R
, during the falling edge of Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an erase, program or write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13. Read data bytes (READ) instruction sequence and data-out sequence
S
0
C
Instruction
24-bit address
(1)
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
DQ0
High Impedance
DQ1
23 22 21
MSB
3
2
1
0
Data out 1
7
6
5
4
3
2
1
0
Data out 2
7
MSB
AI13736b
1. Address bit A23 is don’t care.
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