M36L0T7050T2, M36L0T7050B2
Signal descriptions
2
Signal descriptions
See
and
for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A22)
Addresses A0-A20 are common inputs for the Flash memory and the PSRAM components.
The other lines (A21-A22) are inputs for the Flash memory component only.
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller in the Flash memory, and they select the cells to
be accessed in the PSRAM.
2.2
Data Input/Output (DQ0-DQ15)
In the Flash memory, the Data I/O outputs the data stored at the selected address during a
Bus Read operation or inputs a command or the data to be programmed during a Write Bus
operation.
In the PSRAM DQ0-DQ7 and/or DQ8-DQ15 carry the data to or from the upper and/or lower
part(s) of the selected address during a Write or Read operation, when Upper Byte Enable
(UB
P
) and/or Lower Byte Enable (LB
P
) is/are driven Low.
2.3
Flash Chip Enable (E
F
)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
IL
, and Reset is High, V
IH
, the device is in
active mode. When Chip Enable is at V
IH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is reduced to the standby level.
It is not allowed to set E
F
at V
IL,
E1
P
at V
IL
and E2
P
at V
IH
at the same time.
2.4
Flash Output Enable (G
F
)
The Output Enable input controls data output during Flash memory Bus Read operations.
2.5
Flash Write Enable (W
F
)
The Write Enable controls the Bus Write operation of the Flash memories’ Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
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NUMONYX [ NUMONYX B.V ]
