OXFORD SEMICONDUCTOR LTD.
OXmPCI954
T
ABLE OF
C
ONTENTS
1
2
3
4
4.1
4.2
4.3
PERFORMANCE COMPARISON.......................................................................................................... 6
OXMPCI954 DEVICE MODES............................................................................................................... 8
BLOCK DIAGRAM ................................................................................................................................ 9
PIN INFORMATION—160-PIN LQFP .................................................................................................. 10
MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH THE OX16PCI954. .......................................................... 10
ENHANCED MODES OF OPERATION........................................................................................................................... 11
PIN DESCRIPTIONS......................................................................................................................................................... 12
MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH THE OX16PCI954. .......................................................... 19
ENHANCED MODES OF OPERATION........................................................................................................................... 21
PIN DESCRIPTIONS......................................................................................................................................................... 23
5
5.1
5.2
5.3
PIN INFORMATION—176-PIN VBGA ................................................................................................. 19
6
7
7.1
7.2
7.2.1
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.5
7.6
7.6.1
7.6.2
7.7
7.8
7.9
7.10
CONFIGURATION & OPERATION ..................................................................................................... 30
PCI TARGET CONTROLLER.............................................................................................................. 31
OPERATION ..................................................................................................................................................................... 31
CONFIGURATION SPACE ............................................................................................................................................... 31
PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 32
ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 35
PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 35
PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 36
PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 37
ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 38
LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 38
MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 39
LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 41
LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): ................................................................. 42
UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10)............................................................................................. 44
UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)...................................................................................... 44
UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)............................................................................... 44
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 45
PCI INTERRUPTS............................................................................................................................................................. 47
POWER MANAGEMENT .................................................................................................................................................. 48
POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 48
POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 49
UNIQUE BAR OPTION – FOR FUNCTION 0 ................................................................................................................... 51
MINIPCI SUPPORT – ENHANCED MODES ONLY ......................................................................................................... 52
STANDALONE MODE ...................................................................................................................................................... 56
DEVICE DRIVERS ............................................................................................................................................................ 59
OPERATION – MODE SELECTION ................................................................................................................................. 60
450 MODE..................................................................................................................................................................... 60
550 MODE..................................................................................................................................................................... 60
EXTENDED 550 MODE ................................................................................................................................................ 60
750 MODE..................................................................................................................................................................... 60
650 MODE..................................................................................................................................................................... 60
950 MODE..................................................................................................................................................................... 61
REGISTER DESCRIPTION TABLES ............................................................................................................................... 62
RESET CONFIGURATION ............................................................................................................................................... 66
HARDWARE RESET .................................................................................................................................................... 66
External—Free Release
Page 3
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.3.1
INTERNAL OX16C950 UARTS ........................................................................................................... 60
DS-0019 Jun 05
OXFORD [ OXFORD SEMICONDUCTOR ]
