PE3342
Product Specification
Lock Detect Output
A lock detect signal is provided at pin LD, via the
pin C
EXT
(see Figure 1). C
EXT
is the logical “NAND”
of PD_U and PD_D waveforms, driven through a
series 2k ohm resistor. When the loop is locked,
this output will be HIGH with narrow pulses LOW.
Connecting C
EXT
to an external shunt capacitor
provides integration of this signal.
The C
EXT
signal is sent to the LD pin through an
internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_U
and PD_D.
Serial Data Port
The Serial Data Port allows control data to be
entered into the device. This data can be directed
into one of three registers: the Enhancement
register, the Primary register, and the EE register.
Table 7 defines the control line settings required
to select one of these destinations.
Input data presented on pin 5 (Data) is clocked
serially into the designated register on the rising
edge of Clock. Data is always loaded LSB (B
0
)
first into the receiving register. Figure 4 defines
the timing requirements for this process .
Table 7. Serial Interface
S_WR
0
0
0
E_WR
0
1
X
EELoad
0
0
1
Register Loaded
Primary Register
Enhancement Register
EE Register
Figure 4. Serial Interface Timing Diagram
Data
E_WR
EELoad
t
EC
t
CE
Clock
S_WR
t
DSU
t
DHLD
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
Document No. 70-0091-03
│
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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