PE3342
Product Specification
Functional Description
The PE3342 consists of a dual modulus prescaler,
three programmable counters, a phase detector
and control logic with EEPROM memory (see
Figure 1).
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
state of the internal modulus select logic. The R
and M counters divide the reference and prescaler
outputs by integer values stored in one of three
selectable registers. The modulus select logic
uses the 4-bit A counter.
The phase-frequency detector generates up and
down frequency control signals and are also used
to enable a lock detect circuit.
Frequency control data is loaded into the device
via the Serial Data Port, and can be placed in
three separate frequency registers. One of these
registers (EE register) is used to load from and
write to the non-volatile 20-bit EEPROM.
Various operational and test modes are available
through the enhancement register, which is only
accessible through the Serial Data Port (it cannot
be loaded from the EEPROM).
Main Counter Chain
The main counter chain divides the RF input
frequency, F
in
, by an integer derived from the
user-defined values in the M and A counters. It
operates in two modes:
High Frequency Mode
Setting PB (prescaler bypass) LOW enables the
÷10/11 prescaler, providing operation to 2.7 GHz.
In this mode, the output from the main counter
chain, f
p
, is related to the VCO frequency, F
in
, by
the following equation:
f
p
= F
in
/ [10 x (M + 1) + A]
where 0
≤
A
≤
15 and A
≤
M + 1; 1
≤
M
≤
511
(1)
A consequence of the upper limit on A is that F
in
must be greater than or equal to 90 x (f
r
/ (R+1)) to
obtain contiguous channels. Programming the M
counter with the minimum value of 1 will result in a
minimum M counter divide ratio of 2.
Programming the M and A counters with their
maximum values provides a divide ratio of 5135.
Prescaler Bypass Mode
Setting the PB bit of a frequency register HIGH
allows F
in
to bypass the ÷10/11 prescaler. In this
mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by
the M counter directly. The following equation
relates F
in
to the reference frequency f
r
:
F
in
= (M + 1) x (f
r
/ (R+1))
where 1
≤
M
≤
511
(3)
Reference Counter
The reference counter chain divides the reference
frequency, f
r
, down to the phase detector
comparison frequency, f
c
.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
f
c
= f
r
/ (R + 1)
where 0
≤
R
≤
63
(4)
Note that programming R with 0 will pass the
reference frequency, f
r
, directly to the phase
detector.
Phase Detector
The phase detector is triggered by rising edges
from the main counter (f
p
) and the reference
counter (f
c
). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (f
p
leads f
c
), PD_D pulses
LOW. If the divided reference leads the divided
VCO in phase or frequency (f
c
leads f
p
), PD_U
pulses LOW. The width of either pulse is directly
proportional to the phase offset between the f
p
and
f
c
signals.
When the loop is locked, F
in
is related to the
reference frequency, f
r
, by the following equation:
F
in
= [10 x (M + 1) + A] x (f
r
/ (R+1))
where 0
≤
A
≤
15 and A
≤
M + 1; 1
≤
M
≤
511
(2)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 17
Document No. 70-0091-03
│
UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
