PE3342
Product Specification
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
t
EESU
t
EEPW
t
VPP
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
S_WR pulse width
Clock rising edge to S_WR rising edge
Clock falling edge to E_WR transition
S_WR falling edge to Clock rising edge
E_WR transition to Clock rising edge
(Note 1)
Conditions
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Registers (see Figure 4)
30
30
10
10
30
30
30
30
30
EEPROM Erase/Write Programming (see Figures 5 & 6)
EELoad rising edge to V
PP
rising edge
V
PP
pulse width
V
PP
pulse rise and fall times
(Note 2)
500
25
1
30
ms
µs
Main Divider (Including Prescaler)
F
In
F
In
P
FIn
Operating frequency
Operating frequency
Input level range
Speed-grade option (Note 3)
External AC coupling
300
300
-5
2700
3000
5
MHz
MHz
dBm
Main Divider (Prescaler Bypassed)
F
In
P
FIn
Operating frequency
Input level range
(Note 4)
External AC coupling (Note 4)
50
-5
270
5
MHz
dBm
Reference Divider
f
r
P
fr
Phase Detector
f
c
Comparison frequency
(Note 6)
20
MHz
Operating frequency
Reference input power (Note 4)
(Note 5)
Single ended input
-2
100
MHz
dBm
SSB Phase Noise (F
in
= 1.3 GHz, f
r
= 10 MHz, f
c
= 1.25 MHz, LBW = 70 kHz, V
DD
= 3.0 V, Temp = -40° C
)
100 Hz Offset
1 kHz Offset
Note 1:
Note 2:
Note 3:
Note 4:
-75
-85
dBc/Hz
dBc/Hz
f
Clk
is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f
Clk
specification.
Rise and fall times of the V
PP
programming voltage pulse must be greater than 1
µs.
The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,
Ordering Information, for ordering details.
CMOS logic levels can be used to drive F
In
input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum
of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum
frequency limit exists when operated in this mode.
Note 5:
Note 6:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0091-03
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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