PE43702
Product Specification
Table 5. Control Voltage
State
Low
High
Bias Condition
0 to +1.0 Vdc at 2
µA
(typ)
+2.6 to +5 Vdc at 10
µA
(typ)
Table 9. Serial Attenuation Word Truth Table
Attenuation Word
D7
X
X
D6
L
L
L
L
L
L
L
H
H
D5
L
L
L
L
L
L
H
L
H
D4
L
L
L
L
L
H
L
L
H
D3
L
L
L
L
H
L
L
L
H
D2
L
L
L
H
L
L
L
L
H
D1
L
L
H
L
L
L
L
L
H
D0
(LSB)
L
H
L
L
L
L
L
L
H
Attenuation
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
Table 6. Latch and Clock Specifications
Latch Enable
0
↑
X
X
X
X
X
X
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
D6
L
L
L
L
L
L
L
H
H
X
D5
L
L
L
L
L
L
H
L
H
D4
L
L
L
L
L
H
L
L
H
D3
L
L
L
L
H
L
L
L
H
D2
L
L
L
H
L
L
L
L
H
D1
L
L
H
L
L
L
L
L
H
D0
L
H
L
L
L
L
L
L
H
Attenuation
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
Table 8. Serial Register Map
MSB (last in)
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
LSB (first in)
Q1
D1
Q0
D0
Bits can either be set to logic high or logic low
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:
Attenuation Word: Multiply by 4 and convert to binary
→
4 * 12.5 dB
→
50
→
X0110010
Serial Input: X0110010
Document No. 70-0244-03
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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