PE43702
Product Specification
Figure 15. Serial Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
P/S
TDISU
TDIH
TPSSU
TPSH
D[0]
TCLKL
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
SI
TSISU
TSIH
CLK
LE
TCLKH
TLESU
TLEPW
TPD
VALID
DO[6:0]
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU
TPSH
VALID
DI[6:0]
TDISU
TDIH
LE
TLEPW
VALID
TPD
DO[6:0]
TDIPD
Table 10. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 11. Parallel and Direct Interface AC
Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK
TCLKH
TCLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
-
10
-
MHz
ns
Symbol
Parameter
Min Max Unit
30
30
Latch Enable minimum
pulse width
TLEPW
30
-
ns
-
ns
Last serial clock rising edge
setup time to Latch Enable
rising edge
TDISU
TDIH
TPSSU
TPSIH
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
100
100
100
100
-
-
-
-
ns
ns
ns
ns
TLESU
10
-
ns
TLEPW
TSISU
TSIH
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
30
10
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
-
Digital register delay
(internal)
TDISU
TDIH
Parallel data setup time
Parallel data hold time
Address setup time
100
100
100
100
100
100
-
-
TPD
-
-
10
5
ns
ns
-
Digital register delay
(internal, direct mode only)
TDIPD
TASU
TAH
-
Address hold time
-
TPSSU
TPSH
TPD
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
-
-
10
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
Document No. 70-0244-03 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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